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smsc usb3280 datasheet revision 1.5 (11-15-07) datasheet product features usb3280 hi-speed usb device phy with utmi interface ? available in a 36-pin lead-free rohs compliant (6 x 6 x 0.90mm) qfn package ? interface compliant with the utmi specification (60mhz, 8-bit bidirectional interface) ? only one required power supply (+3.3v) ? usb-if ?hi-speed? certified to usb 2.0 electrical specification ? supports 480mbps hi-speed (hs) and 12mbps full speed (fs) serial data transmission rates ? integrated 45 and 1.5k termination resistors reduce external component count ? internal short circuit protection of dp and dm lines ? on-chip oscillator operates with low cost 24mhz crystal ? latch-up performance exceeds 150ma per eia/jesd 78, class ii ? esd protection levels of 5kv hbm without external protection devices ? sync and eop generation on transmit packets and detection on receive packets ? nrzi encoding and decoding ? bit stuffing and unstuffing with error detection ? supports the usb suspend state, hs detection, hs chirp, reset and resume ? support for all test modes defined in the usb 2.0 specification ? 55ma unconfigured current (typical) - ideal for bus powered applications. ? 83ua suspend current (typical) - ideal for battery powered applications. ? industrial operating temperature -40 o c to +85 o c applications the usb3280 is the ideal companion to any asic, soc or fpga solution designed with a utmi hi-speed usb device (peripheral) core. the usb3280 is well suited for: ? cell phones ? mp3 players ? scanners ? external hard drives ? digital still and video cameras ? portable media players ? entertainment devices ? printers
order number(s): usb3280-aezg for 36-pin, qfn le ad-free rohs compliant package USB3280-AEZG-TR for 36-pin, qfn lead-free rohs compli ant package (tape and reel) reel size is 3000 pieces. hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 2 smsc usb3280 datasheet 80 arkay drive, hauppauge, ny 11788 (631) 435-6000, fax (631) 273-3123 copyright ? 2007 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc produc ts are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and produc t descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this inform ation does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporat ion (?smsc?). product names and company na mes are the trademarks of their respective holders. smsc disclaims and excludes any and all warrant ies, including without limi tation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, a nd against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of wa rranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages.
hi-speed usb device phy with utmi interface datasheet smsc usb3280 3 revision 1.5 (11-15-07) datasheet table of contents chapter 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 chapter 2 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 chapter 3 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 chapter 4 interface signal definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 chapter 5 limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 chapter 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 driver characteristics of full-speed drivers in high-speed capable transceivers . . . . . . . . . . . . 16 6.2 high-speed signaling eye patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 chapter 7 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2 system clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.3 clock and data re covery circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.4 tx logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.5 rx logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.6 usb 2.0 transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.6.1 high speed and full speed transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.6.2 termination resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.6.3 bias generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.7 crystal oscillator and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.8 internal regulators and por . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.8.1 internal regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.8.2 power on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.8.3 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 chapter 8 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 linestate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.2 opmodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3 test mode support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.4 se0 handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.5 reset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.6 suspend detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.7 hs detection handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.8 hs detection handshake ? fs downstream facing port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.9 hs detection handshake ? hs downstream facing port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.10 hs detection handshake ? suspend timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.11 assertion of resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.12 detection of resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.13 hs device attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.14 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 chapter 9 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 4 smsc usb3280 datasheet list of figures figure 2.1 usb3280 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3.1 usb3280 pinout - top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3.2 usb3280 pinout - bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 6.1 full-speed driver voh/io h characteristics for high-speed ca pable transceiver . . . . . . . . 17 figure 6.2 full-speed driver vol/iol characteristics for high-speed capa ble transceiver. . . . . . . . . 17 figure 6.3 eye pattern measurement planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6.4 eye pattern for transmit waveform and eye patter n definition . . . . . . . . . . . . . . . . . . . . . . 19 figure 6.5 eye pattern for receive waveform and eye pattern definition . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7.1 fs clk relationship to transmit data and control signals . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7.2 fs clk relationship to receiv e data and control signals. . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7.3 transmit timing for a data packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7.4 receive timing for data with unst uffed bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 7.5 receive timing for a handshake packet (no crc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7.6 receive timing for setup packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 7.7 receive timing for data packet (with crc-16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 8.1 reset timing behavior (hs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 8.2 suspend timing behavior (hs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 8.3 hs detection handshake timing behavior (fs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 8.4 chirp k-j-k-j-k-j sequence dete ction state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 8.5 hs detection handshake timing behavior (hs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 8.6 hs detection handshake timing behavior from susp end . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 8.7 resume timing behavior (hs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 figure 8.8 device attach behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 8.9 usb3280 application diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 9.1 usb3280-aezg 36-pin qfn package outline and parameters, 6 x 6 x 0.90 mm body (lead- free rohs compliant) 42 figure 9.2 qfn, 6x6 tape & reel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 9.3 reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
hi-speed usb device phy with utmi interface datasheet smsc usb3280 5 revision 1.5 (11-15-07) datasheet list of tables table 4.1 system interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4.2 data interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4.3 usb i/o signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4.4 biasing and clock oscillator signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4.5 power and ground signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5.3 recommended external clock conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6.1 electrical characte ristics: supply pins ( note 6.1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6.2 dc electrical characteristics: logic pins ( note 6.2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6.3 dc electrical characteri stics: analog i/o pins (dp/dm) ( note 6.3 ) . . . . . . . . . . . . . . . . . . . . 14 table 6.4 dynamic characteristic s: analog i/o pins (dp/dm) ( note 6.4 ) . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6.5 dynamic characterist ics: digital utmi pins ( note 6.5 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7.1 dp/dm termination vs. signaling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8.1 linestate states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8.2 operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8.3 usb 2.0 test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8.4 reset timing values (hs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8.5 suspend timing values (hs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8.6 hs detection handshake timing values (fs mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8.7 reset timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 8.8 hs detection handshake timing values from suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 8.9 resume timing values (hs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 8.10 attach and reset timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 6 smsc usb3280 datasheet chapter 1 general description the usb3280 provides the physical layer (phy) interface to a usb 2.0 device controller. the ic is available in a 36-pin lead-free rohs compliant qfn package. 1.1 product description the usb3280 is an industrial temperature usb 2.0 ph ysical layer transceiver (phy) integrated circuit. smsc?s proprietary technology results in low power dissipation, which is ideal for building a bus powered usb 2.0 peripheral. the phy uses an 8-bit bidirectional parallel interface, which complies with the usb transceiver macrocell interface (utmi) s pecification. it supports 480mbps transfer rate, while remaining backward compatible with usb 1.1 legacy protocol at 12mbps. all required termination and 5.25v short circuit protec tion of the dp/dm lines are internal to the chip. the usb3280 also has an integrated 1.8v regula tor so that only a 3.3v supply is required. while transmitting data, the phy serializes data and generates sync and eop fields. it also performs needed bit stuffing and nrzi encoding. likewise, while receiving data, the phy de-serializes incoming data, stripping sync and eop fields and per forms bit un-stuffing and nrzi decoding.
hi-speed usb device phy with utmi interface datasheet smsc usb3280 7 revision 1.5 (11-15-07) datasheet chapter 2 functional block diagram figure 2.1 usb3280 block diagram pwr control fs se+ r x utmi interface tx state machine parallel to serial conversion bit stuff nrzi encode tx logic clock recovery unit clock and data recovery elasticity buffer vp vm biasing bandgap voltage reference current reference rbias vdd3.3 pll and xtal osc system clocking fs rx fs se- hs rx hs sq rx state machine serial to parallel conversion bit unstuff nrzi decode rx logic dm tx 1.5k fs tx hs tx hs_data hs_cs_enable hs_drive_enable oeb vmo vpo rpu_en mux dp r x v a l i d r x a c t i v e r x e r r o r t x r e a d y reset suspendn xcvrselect termselect o p m o d e [ 1 : 0 ] linestate[1:0] clkout txvalid d a t a [ 7 : 0 ] xi xo 1.8v regulator
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 8 smsc usb3280 datasheet chapter 3 pinout the flag of the qfn package must be connected to ground. figure 3.1 usb3280 pinout - top view figure 3.2 usb3280 pinout - bottom view 1 2 3 4 5 6 7 8 9 termselect txready suspendn txvalid reset vdd3.3 dp dm xcvrselect usb2.0 usb3280 phy ic clkout vdd1.8 vdd3.3 vdd3.3 rxactive opmode0 linestate1 linestate0 opmode1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 data[6] data[7] rxvalid data[0] data[5] data[2] data[3] data[4] data[1] 28 29 30 31 32 34 35 36 33 reg_en rbias vdd3.3 vdda1.8 xi xo vdd1.8 vdd3.3 rxerro r exposed gnd pad
hi-speed usb device phy with utmi interface datasheet smsc usb3280 9 revision 1.5 (11-15-07) datasheet chapter 4 interface signal definition table 4.1 system interface signals name direction active level description reset (rst) input high reset. reset all state machines. after coming out of reset, must wait 5 rising edges of clock before asserting txvalid for transmit. see section 7.8.3 xcvrselect (xsel) input n/a transceiver select. this signal selects between the fs and hs transceivers: 0: hs transceiver enabled 1: fs transceiver enabled. termselect (tsel) input n/a termination select. this signal selects between the fs and hs terminations: 0: hs termination enabled 1: fs termination enabled suspendn (spdn) input low suspend. places the transceiver in a mode that draws minimal power from supplies. shuts down all blocks not necessary for suspend/resume operation. while suspended, termselect must always be in fs mode to ensure that the 1.5k pull-up on dp remains powered. 0: transceiver circuitry drawing suspend current 1: transceiver circuitry drawing normal current clkout (clk) output rising edge system clock . this output is used for clocking receive and transmit parallel data at 60mhz. opmode[1:0] (om1) (om0) input n/a operational mode. these signals select between the various operational modes: [1] [0] description 0 0 0: normal operation 0 1 1: non-driving (all terminations removed) 1 0 2: disable bit stuffing and nrzi encoding 1 1 3: reserved linestate[1:0] (ls1) (ls0) output n/a line state . these signals reflect the current state of the usb data bus in fs mode, with [0] reflecting the state of dp and [1] reflecting the state of dm. when the device is suspended or resuming from a suspended state, the signals are combinatorial. otherwise, the signals are synchronized to clkout. [1] [0] description 0 0 0: se0 0 1 1: j state 1 0 2: k state 1 1 3: se1
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 10 smsc usb3280 datasheet table 4.2 data interface signals name direction active level description data[7:0] (d7) . . . (d0) bidirectional high data bus. 8-bit bidirectional mode. txvalid data[7:0] 0 output 1 input txvalid (txv) input high transmit valid. indicates that the data bus is valid for transmit. the assertion of txvalid initiates the transmission of sync on the usb bus. the negation of txvalid initiates eop on the usb. control inputs (opmode[1:0], termselect,xcvrselect) must not be changed on the de-assertion or assertion of txvalid. the phy must be in a quiescent state when these inputs are changed. txready (txr) output high transmit data ready. if txvalid is assert ed, the sie must always have data available for clocking into the tx holding register on the rising edge of clkout. txready is an acknowledgement to the sie that the transceiver has clocked the data from the bus and is ready for the next transfer on t he bus. if txvalid is negated, txready can be ignored by the sie. rxvalid (rxv) output high receive data valid. indicates that the data bus has received valid data. the receive data holding register is full and ready to be unloaded. the sie is expected to latch the data bus on the rising edge of clkout. rxactive (rxa) output high receive active. indicates that the receive state machine has detected start of packet and is active. rxerror (rxe) output high receive error . 0: indicates no error. 1: indicates a receive error has been detected. this output is clocked with the same timing as the receive data lines and can occur at anytime during a transfer. table 4.3 usb i/o signals name direction active level description dp i/o n/a usb positive data pin. dm i/o n/a usb negative data pin. table 4.4 biasing and clock oscillator signals name direction active level description rbias (rb) input n/a external 1% bias resistor. requires a 12k ? resistor to ground. used for setting hs transmit current level and on-chip termination impedance. xi/xo input n/a external crystal. 24mhz crystal connected from xi to xo.
hi-speed usb device phy with utmi interface datasheet smsc usb3280 11 revision 1.5 (11-15-07) datasheet table 4.5 power and ground signals name direction active level description vdd3.3 (v33) n/a n/a 3.3v supply. provides power for usb 2.0 transceiver, utmi+ digital, digital i/o, and regulators. reg_en (ren) input high on-chip 1.8v regulator enable. connect to ground to disable both of the on chip (vdda1.8 and vdd1.8) regulators. when regulators are disabled: ? external 1.8v must be supplied to vdda1.8 and vdd1.8 pins. when the regulators are disabled, vdda1.8 may be connected to vdd1.8 and a bypass capacitor (0.1 f recommended) should be connected to each pin. ? the voltage at vdd3.3 must be at least 2.64v (0.8 * 3.3v) before voltage is applied to vdda1.8 and vdd1.8. vdd1.8 (v18) n/a n/a 1.8v digital supply. supplied by on-chip regulator when reg_en is active. low esr 4.7uf minimum capacitor requirement when using internal regulators. do not connect vdd1.8 to vdda1.8 when using internal regulators. when the regulators are disabled, vdd1.8 may be connected to vdd1.8a. vss (gnd) n/a n/a common ground. vdda1.8 (v18a) n/a n/a 1.8v analog supply. supplied by on-chip regulator when reg_en is active. low esr 4.7uf minimum capacitor requirement when using internal regulators. do not connect vdd1.8a to vdd1.8 when using internal regulators. when the regulators are disabled, vdd1.8a may be connected to vdd1.8.
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 12 smsc usb3280 datasheet chapter 5 limiting values note: in accordance with the absolute maximum rating system (iec 60134) table 5.1 absolute maximum ratings parameter symbol conditions min typ max units maximum dp and dm voltage to ground v max_5v -0.3 5.5 v maximum vdd1.8 and vdda1.8 voltage to ground v max_1.8v -0.3 2.5 v maximum 3.3v supply voltage to ground v max_3.3v -0.3 4.0 v maximum i/o voltage to ground v i -0.3 4.0 v storage temperature t stg -55 150 o c esd performance all pins v hbm human body model 5 kv latch-up performance all pins i ltch_up eia/jesd 78, class ii 150 ma table 5.2 recommended operating conditions parameter symbol conditi ons min typ max units 3.3v supply voltage (vdd3.3 and vdda3.3) v dd3.3 3.0 3.3 3.6 v input voltage on digital pins v i 0.0 v dd3.3 v input voltage on analog i/o pins (dp, dm) v i(i/o) 0.0 v dd3.3 v ambient temperature t a -40 85 o c table 5.3 recommended external clock conditions parameter symbol conditions min typ max units system clock frequency xo driven by the external clock; and no connection at xi 24 (100ppm) mhz system clock duty cycle xo driven by the external clock; and no connection at xi 45 50 55 %
hi-speed usb device phy with utmi interface datasheet smsc usb3280 13 revision 1.5 (11-15-07) datasheet chapter 6 electrical characteristics note 6.1 v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = -40 o c to 85 o c; unless otherwise specified. note 6.2 v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = -40 o c to 85 o c; unless otherwise specified. table 6.1 electrical characteristics: supply pins ( note 6.1 ) parameter symbol conditi ons min typ max units unconfigured current i avg(ucfg) device unconfigured 55 ma fs idle current i avg(fs) fs idle not data transfer 55 ma fs transmit current i avg(fstx) fs current during data transmit 60.5 ma fs receive current i avg(fsrx) fs current during data receive 57.5 ma hs idle current i avg(hs) hs idle not data transfer 60.6 ma hs transmit current i avg(hstx) hs current during data transmit 62.4 ma hs receive current i avg(hsrx) hs current during data receive 61.5 ma low power mode i dd(lpm) vbus 15k ? pull-down and 1.5k ? pull-up resistor currents not included. 83 ua table 6.2 dc electrical char acteristics: logic pins ( note 6.2 ) parameter symbol conditions min typ max units low-level input voltage v il v ss 0.8 v high-level input voltage v ih 2.0 v dd3.3 v low-level output voltage v ol i ol = 8ma 0.4 v high-level output voltage v oh i oh = -8ma v dd3.3 - 0.5 v input leakage current i li 1 ua pin capacitance cpin 4 pf
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 14 smsc usb3280 datasheet table 6.3 dc electrical characteris tics: analog i/o pins (dp/dm) ( note 6.3 ) parameter symbol conditions min typ max units fs functionality input levels differential receiver input sensitivity v difs | v(dp) - v(dm) | 0.2 v differential receiver common-mode voltage v cmfs 0.8 2.5 v single-ended receiver low level input voltage v ilse 0.8 v single-ended receiver high level input voltage v ihse 2.0 v single-ended receiver hysteresis v hysse 0.050 0.150 v output levels low level output voltage v fsol pull-up resistor on dp; r l = 1.5k to v dd3.3 0.3 v high level output voltage v fsoh pull-down resistor on dp, dm; r l = 15k to gnd 2.8 3.6 v termination driver output impedance for hs and fs z hsdrv steady state drive (see figure 6.1 ) 40.5 45 49.5 input impedance z inp tx, rpu disabled 10 m pull-up resistor impedance z pu bus idle 0.900 1.24 1.575 k ? pull-up resistor impedance z purx device receiving 1.425 2.26 3.09 k ? termination voltage for pull- up resistor on pin dp v term 3.0 3.6 v hs functionality input levels hs differential input sensitivity v dihs | v(dp) - v(dm) | 100 mv hs data signaling common mode voltage range v cmhs -50 500 mv hs squelch detection threshold (differential) v hssq squelch threshold 100 mv unsquelch threshold 150 mv output levels high speed low level output voltage (dp/dm referenced to gnd) v hsol 45 load -10 10 mv
hi-speed usb device phy with utmi interface datasheet smsc usb3280 15 revision 1.5 (11-15-07) datasheet note 6.3 v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = -40 o c to 85 o c; unless otherwise specified. note 6.4 v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = -40 o c to 85 o c; unless otherwise specified. high speed high level output voltage (dp/dm referenced to gnd) v hsoh 45 load 360 440 mv high speed idle level output voltage (dp/dm referenced to gnd) v olhs 45 load -10 10 mv chirp-j output voltage (differential) v chirpj hs termination resistor disabled, pull-up resistor connected. 45 load. 700 1100 mv chirp-k output voltage (differential) v chirpk hs termination resistor disabled, pull-up resistor connected. 45 load. -900 -500 mv leakage current off-state leakage current i lz 1 ua port capacitance transceiver input capacitance c in pin to gnd 5 10 pf table 6.4 dynamic characteristi cs: analog i/o pins (dp/dm) ( note 6.4 ) parameter symbol conditions min typ max units fs output driver timing rise time t fsr c l = 50pf; 10 to 90% of |v oh - v ol | 420ns fall time t fff c l = 50pf; 10 to 90% of |v oh - v ol | 420ns output signal crossover voltage v crs excluding the first transition from idle state 1.3 2.0 v differential rise/fall time matching frfm excluding the first transition from idle state 90 111.1 % hs output driver timing differential rise time t hsr 500 ps differential fall time t hsf 500 ps driver waveform requirements eye pattern of template 1 in usb 2.0 specification see figure 6.2 high speed mode timing receiver waveform requirements eye pattern of template 4 in usb 2.0 specification see figure 6.2 data source jitter and receiver jitter tolerance eye pattern of template 4 in usb 2.0 specification see figure 6.2 table 6.3 dc electrical characterist ics: analog i/o pins (dp/dm) ( note 6.3 ) (continued) parameter symbol conditions min typ max units
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 16 smsc usb3280 datasheet note 6.5 v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = -40 o c to 85 o c; unless otherwise specified. 6.1 driver characteristics of full -speed drivers in high-speed capable transceivers the usb3280 uses a differential output driver to drive the usb data signal onto the usb cable. figure 6.1 full-speed driver voh/ioh characteristics for high-speed capable transceiveron page 17 shows the v/i characteristics for a full-speed driver which is part of a high-speed capable transceiver. the normalized v/i curve for the driver must fall entirely inside the shaded region. the v/i region is bounded by the minimum driver impedance above (4 0.5 ohm) and the maximum driver impedance below (49.5 ohm). the output volt age must be within 10mv of grou nd when no current is flowing in or out of the pin. table 6.5 dynamic characteristics: digital utmi pins ( note 6.5 ) parameter symbol conditions min typ max units utmi timing data[7:0] t pd output delay. measured from phy output to the rising edge of clkout 25ns rxvalid rxactive rxerror linestate[1:0] txready data[7:0] t su setup time. measured from phy input to the rising edge of clkout. 5ns txvalid opmode[1:0] xcvrselect termselect data[7:0] t h hold time. measured from the rising egde of clkout to the phy input signal edge. 0ns txvalid opmode[1:0] xcvrselect termselect
hi-speed usb device phy with utmi interface datasheet smsc usb3280 17 revision 1.5 (11-15-07) datasheet figure 6.1 full-speed driver voh/ioh charac teristics for high-speed capable transceiver figure 6.2 full-speed driver vol/iol characte ristics for high-speed capable transceiver v out (volts) v oh 0 0 drive high 0.698*v oh test limit slope = 1/49.5 ohm slope = 1/40.5 ohm 0.566*v oh -10.71 * |v oh | -6.1 * |v oh | i out (ma) v out (volts) v oh 0 0 drive low i out (ma) 22 1.09v 0.434*v oh test limit slope = 1/40.5 ohm slope = 1/49.5 ohm 10.71 * |v oh |
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 18 smsc usb3280 datasheet 6.2 high-speed sign aling eye patterns high-speed usb signals are characterized using eye patterns. for measuri ng the eye patterns 4 points have been defined (see figure 6.3 ). the universal serial bus specification rev.2.0 defines the eye patterns in several ?templates?. the two temp lates that are relevant to the phy are shown below. figure 6.3 eye pattern measurement planes usb cable transceiver device circuit board transceiver hub circuit board connector traces traces a connector b tp1 tp2 tp3 tp4
hi-speed usb device phy with utmi interface datasheet smsc usb3280 19 revision 1.5 (11-15-07) datasheet the eye pattern in figure 6.4 defines the transmit waveform requir ements for a hub (measured at tp2 of figure 6.3 ) or a device without a captiv e cable (measured at tp3 of figure 6.3 ). the corresponding signal levels and timings are given in table below. ti me is specified as a perc entage of the unit interval (ui), which represents the nominal bit duration for a 480 mbit/s transmission rate. figure 6.4 eye pattern for transmit waveform and eye pattern definition voltage level (d+, d-) time (% of unit interval) level 1 525mv in ui following a transition, 475mv in all others n/a level 2 -525mv in ui following a transition, -475mv in all others n/a point 1 0v 7.5% ui point 2 0v 92.5% ui point 3 300mv 37.5% ui point 4 300mv 62.5% ui point 5 -300mv 37.5% ui point 6 -300mv 62.5% ui differential -400mv differential 400mv unit interval 100% level 2 level 1 point 1 point 2 point 4 point 3 point 6 point 5 0% 0 volts differential
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 20 smsc usb3280 datasheet the eye pattern in figure 6.5 defines the receiver sensitivity r equirements for a hub (signal applied at test point tp2 of figure 6.3 ) or a device without a captive cable (signal applied at test point tp3 of figure 6.3 ). the corresponding signal levels and timings are given in the table below. timings are given as a percentage of the unit interval (ui), wh ich represents the nominal bit duration for a 480 mbit/s transmission rate. figure 6.5 eye pattern for receive waveform and eye pattern definition voltage level (d+, d-) time (% of unit interval) level 1 575mv n/a level 2 -575mv n/a point 1 0v 15% ui point 2 0v 85% ui point 3 150mv 35% ui point 4 150mv 65% ui point 5 -150mv 35% ui point 6 -150mv 65% ui point 1 0% 100% point 2 level 2 level 1 point 3 point 4 point 5 point 6 differential -400mv differential 400mv differential 0 volt
hi-speed usb device phy with utmi interface datasheet smsc usb3280 21 revision 1.5 (11-15-07) datasheet chapter 7 functional overview figure 2.1 on page 7 shows the functional block diagram of the usb3280. each of the functions is described in detail below. 7.1 modes of operation the usb3280 supports an 8-bit bi-directional parallel interface. ? clkout runs at 60mhz ? the 8-bit data bus (data[7:0]) is used for transmit when txvalid = 1 ? the 8-bit data bus (data[7:0]) is used for receive when txvalid = 0 7.2 system clocking this block connects to either an external 24mhz crystal or an external clock source and generates a 480mhz multi-phase clock. the clock is used in the crc block to over-sample the incoming received data, resynchronize the transmit data, and is divided down to 60mhz (clkout) which acts as the system byte clock. the pll block also outputs a clock valid signal to the other parts of the transceiver when the clock signal is stable. all utmi signals are synchronized to the clkout output. the behavior of the clkout is as follows: ? produce the first clkout transition no later th an 5.6ms after negation of suspendn. the clkout signal frequency error is less than 10% at this time. ? the clkout signal will fully meet the required accuracy of 500ppm no later than 1.4ms after the first transition of clkout. in hs mode there is one clkout cycle per byte time. the frequency of clkout does not change when the phy is switched between hs to fs mode s. in fs mode there are 5 clkout cycles per fs bit time, typically 40 clkout cycles per fs byte time. if a received byte co ntains a stuffed bit then the byte boundary can be stretche d to 45 clkout cycles, and two st uffed bits would result in a 50 clkout cycles. figure 7.1 shows the relationship between clkout and the transmit data transfer signals in fs mode. txready is only asserted for one clkout per byte time to signal the sie that the data on the data lines has been read by the phy. the sie may hold the data on the data lines for the duration of the byte time. transitions of txvalid must meet the defined setup and hold times relative to clkout. figure 7.1 fs clk relationship to transmit data and control signals
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 22 smsc usb3280 datasheet figure 7.2 shows the relationship between clkout and t he receive data control signals in fs mode. rxactive "frames" a packet, transitioning only at the beginning and end of a packet. however transitions of rxvalid may take place an y time 8 bits of data are available. figure 7.1 also shows how rxvalid is only asserted for one clkout cycle per byte time even though the data may be presented for the full byte time. the xcvrselect signal determines whether the hs or fs timing relationship is applied to the data and control signals. 7.3 clock and data recovery circuit this block consists of the clock and data recovery circuit and the elasticity buffer. the elasticity buffer is used to compensate for differences bet ween the transmitting and receiving clock domains. the usb 2.0 specification def ines a maximum clock error of 1000ppm of drift. 7.4 tx logic this block receives parallel data bytes placed on the data bus and performs the necessary transmit operations. these operations include parallel to serial conversion, bit stuffing and nrzi encoding. upon valid assertion of the proper tx control lines by the sie and tx stat e machine, the tx logic block will synchronously shift, at either the fs or hs rate, the data to the fs/hs tx block to be transmitted on the usb cable. data transmit timing is shown in figure 7.3 . figure 7.2 fs clk relationship to receive data and control signals figure 7.3 transmit timing for a data packet
hi-speed usb device phy with utmi interface datasheet smsc usb3280 23 revision 1.5 (11-15-07) datasheet the behavior of the transmit state machine is described below. ? asserting a reset forces the transmit state machine into the reset state which negates txready. when reset is negated the transm it state machine will enter a wait state. ? the sie asserts txvalid to begin a transmission. ? after the sie asserts txvalid it can assume that the transmission has started when it detects txready has been asserted. ? the sie must assume that t he usb3280 has consumed a data byte if txready and txvalid are asserted on the rising edge of clkout. ? the sie must have valid packet information (pid) asserted on the data bus coincident with the assertion of txvalid. ? txready is sampled by the sie on the rising edge of clkout. ? the sie negates txvalid to complete a packet. once negated, the transmit logic will never reassert txready until after the eop has been generated. (txready will not re-assert until txvald asserts again. ? the usb3280 is ready to transmit another packet immediately, however the sie must conform to the minimum inter-p acket delays identified in the usb 2.0 specification. 7.5 rx logic this block receives serial data from the crc blo ck and processes it to be transferred to the sie on the data bus. the processing involved includes nrzi decoding, bit unstuffing, and serial to parallel conversion. upon valid assertion of the proper rx control lines by the rx st ate machine, the rx logic block will provide bytes to the data bus as shown in the figures below. the behavior of the receive state machine is described below. the assertion of reset will force the receive state machine into the reset state. the reset state deasserts rxactive and rxvalid. when the reset signal is deasserted the receive state machine enters the rx wait state and starts looking for a sync pattern on the usb. when a sync pattern is detected the state machine will enter the strip sync state and assert rxactive. the length of the received hi-speed sync pattern varies and can be up to 32 bits long or as short as 12 bits long when at the end of five hubs. as a result, the state machine may remain in the strip sync state for several byte times before capturing the first byte of data and entering the rx data state. after valid serial data is received, the state machine enters the rx data state, where the data is loaded into the rx holding register on the rising edge of clkout and rxvalid is asserted. the sie must clock the data off the data bus on the next ri sing edge of clkout. if opmode = normal, then stuffed bits are stripped from the data stream. each time 8 stuffed bits are accumulated the state machine will enter the rx data wait state, negating rxvalid thus skipping a byte time. figure 7.4 receive timing fo r data with unstuffed bits
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 24 smsc usb3280 datasheet when the eop is detected the state machine will enter the strip eop state and negate rxactive and rxvalid. after the eop has been stripped the receive state machine will reenter the rx wait state and begin looking for the next packet. the behavior of the receive state machine is described below: ? rxactive and rxready are sampled on the rising edge of clkout. ? in the rx wait state the receiver is always looking for sync. ? the usb3280 asserts rxactive when sync is detected (strip sync state). ? the usb3280 negates rxactive when an eop is de tected and the elasticity buffer is empty (strip eop state). ? when rxactive is asserted, rxvalid will be a sserted if the rx holding register is full. ? rxvalid will be negated if the rx holding regist er was not loaded during the previous byte time. this will occur if 8 stuffed bits have been accumulated. ? the sie must be ready to consume a data byte if rxactive and rxvalid are asserted (rx data state). ? figure 7.5 shows the timing relationship between the received data (dp/dm), rxvalid, rxactive, rxerror and data signals. notes: ? the usb 2.0 transceiver does not decode packet id's (pids). they are passed to the sie for decoding. ? figure 7.5 , figure 7.6 and figure 7.7 are timing examples of a hs/fs phy when it is in hs mode. when a hs/fs phy is in fs mode there are appr oximately 40 clkout cycles every byte time. the receive state machine assumes that the sie captures the data on the data bus if rxactive and rxvalid are asserted. in fs mode, rxvalid will only be asserted for one clkout per byte time. ? in figure 7.5 , figure 7.6 and figure 7.7 the sync pattern on dp/dm is shown as one byte long. the sync pattern received by a device can vary in length. these figures assume that all but the last 12 bits have been consumed by the hubs between the device and the host controller. figure 7.5 receive timing for a handshake packet (no crc)
hi-speed usb device phy with utmi interface datasheet smsc usb3280 25 revision 1.5 (11-15-07) datasheet the receivers connect directly to the usb cable. the block contains a separate differential receiver for hs and fs mode. depending on the mode, the se lected receiver provides the serial data stream through the mulitplexer to the rx logic block. the fs mode section of the fs/hs rx block also consists of a single-ended receiver on each of the data lines to determine the correct fs linestate. for hs mode support, the fs/hs rx block contains a squelch circuit to insure that noise is never interpreted as data. figure 7.6 receive timing for setup packet figure 7.7 receive timing for data packet (with crc-16)
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 26 smsc usb3280 datasheet 7.6 usb 2.0 transceiver the smsc hi-speed usb 2.0 transceiver consists of the high speed and full speed transceivers, and the termination resistors. 7.6.1 high speed and full speed transceivers the usb3280 transceiver meets all requ irements in the usb 2.0 specification. the receivers connect directly to the usb cable. th is block contains a separate differential receiver for hs and fs mode. depending on the mode, the se lected receiver provides the serial data stream through the multiplexer to the rx logic block. the fs mode section of the fs/hs rx block also consists of a single-ended receiver on each of the data lines to determine the correct fs linestate. for hs mode support, the fs/hs rx block contains a squelch circuit to insure that noise is never interpreted as data. the transmitters connect directly to the usb cable. the block contains a separate differential fs and hs transmitter which receive encoded, bit stuffed, serialized data from the tx logic block and transmit it on the usb cable. 7.6.2 termination resistors the usb3280 transceiver fully integrates all of th e usb termination resistors. the usb3280 includes the 1.5k ? pull-up resistor on dp. in addition the 45 ? high speed termination resistors are also integrated. these integrated resist ors require no tuning or trimming. the state of the resistors is determined by the operating mode of the phy. the possible valid resistor combinations are shown in table 7.1 . ? rpu_dp_en activates the 1.5k ? dp pull-up resistor ? hsterm_en activates the 45 ? dp and dm high speed termination resistors table 7.1 dp/dm termination vs. signaling mode signaling mode utmi+ interface settings resistor settings xcvrselect termselect opmode[1:0] rpu_dp_en hsterm_en tri-state drivers xb xb 01b 0b 0b power-up 1b 0b 00b 0b 0b peripheral chirp 0b 1b 10b 1b 0b peripheral hs 0b 0b 00b 0b 1b peripheral fs 1b 1b 00b 1b 0b peripheral hs/fs suspend 1b 1b 00b 1b 0b peripheral hs/fs resume 1b 1b 10b 1b 0b peripheral test j/test k 0b 0b 10b 0b 1b
hi-speed usb device phy with utmi interface datasheet smsc usb3280 27 revision 1.5 (11-15-07) datasheet 7.6.3 bias generator this block consists of an internal bandgap refe rence circuit used for generating the high speed driver currents and the biasing of the analog circuits. this block requires an external 12k , 1% tolerance, external reference resistor c onnected from rbias to ground. 7.7 crystal oscillator and pll the usb3280 uses an internal crystal driver and pll sub-system to provide a clean 480mhz reference clock that is used by the phy during both transmi t and receive. the usb3280 requires a clean 24mhz crystal or clock as a frequency reference. if the 24mhz reference is noisy or off frequency the phy may not operate correctly. the usb3280 can use either a crystal or an extern al clock oscillator for the 24mhz reference. the crystal is connected to the xi and xo pins as shown in the application diagram, figure 8.9 . if a clock oscillator is used the clock should be connected to the xi input and the xo pin left floating. when a external clock is used the xi pin is designed to be driven with a 0 to 3.3 volt signal. when using an external clock the user needs to take care to ens ure the external clock source is clean enough to not degrade the high speed eye performance. once, the 480mhz pll has locked to the correct fr equency it will drive the clkout pin with a 60mhz clock. 7.8 internal regulators and por the usb3280 includes an integrated set of bui lt in power management functions. these power management features include a por generation and allow the usb3280 to be powered from a single 3.3 volt power supply. this reduces the bill of materials and simplifies product design. 7.8.1 internal regulators the usb3280 has two integrated 3.3 volt to 1.8 vo lt regulators. these regulators require an external 4.7uf +/-20% low esr bypass capaci tor to ensure stability. x5r or x7r ceramic capacitors are recommended since they exhibit an esr lower t han 0.1 ohm at frequencies greater than 10khz. the two regulator outputs, which require bypass capacitors, are the pins labeled vdda1.8 and vdd1.8. each pin requires a 4.7uf bypass capacitor placed as close to the pin as possible. note: the usb3280 regulators are designed to generate a 1.8 volt supply for the usb3280 only. using the regulators to provide current for other circuits is not recommended and smsc does not guarantee usb performance or regulator stability. 7.8.2 power on reset (por) the usb3280 provides an internal por circuit that generates a reset pulse once the phy supplies are stable. 7.8.3 reset pin the utmi+ digital can be reset at any time with the reset pin. the reset pin of the usb3280 may be asynchronously asserted and de-asserted so long as it is held in the asserted state continuously for a duration greater than one clkout cycle. the r eset input may be asserted when the usb3280 clkout signal is not active (i.e. in the susp end state caused by asserting the suspendn input) but reset must only be de-asserted when the usb3280 cl kout signal is active and the reset has been held asserted for a duration greater than one ckout clock cycle. no other phy digital input signals may change state for two clkout clock cycles after the de-assertion of the reset signal.
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 28 smsc usb3280 datasheet chapter 8 application notes the following sections consist of se lect functional explanations to aid in implementing the usb3280 into a system. for complete descripti on and specifications consult the usb 2.0 transceiver macrocell interface specification and universal serial bus specification revision 2.0. 8.1 linestate the voltage thresholds that the li nestate[1:0] signals use to reflec t the state of dp and dm depend on the state of xcvrselect. linestate[1:0] us es hs thresholds when the hs transceiver is enabled (xcvrselect = 0) and fs thresholds when the fs transceiver is enabled (xcvrselect = 1). there is not a concept of variable single-e nded thresholds in the usb 2.0 specification for hs mode. the hs receiver is used to detect chirp j or k, wher e the output of the hs receiver is always qualified with the squelch signal. if squelched, the output of the hs receiver is ignored. in the usb3280, as an alternative to using variable thresholds for the single-ended receivers, the following approach is used. in hs mode, 3ms of no usb activity (idle state) signals a reset. the sie monitors linestate[1:0] for the idle state. to minimize transitions on linestate[1:0] while in hs mode, the presence of !squelch is used to force linestate[1:0] to a j state. table 8.1 linestate states state of dp/dm lines linestate[1:0] full speed xcvrselect =1 termselect=1 high speed xcvrselect =0 termselect=0 chirp mode xcvrselect =0 termselect=1 ls[1] ls[0] 0 0 se0 squelch squelch 0 1 j !squelch !squelch & hs differential receiver output 1 0 k invalid !squelch & !hs differential receiver output 1 1 se1 invalid invalid
hi-speed usb device phy with utmi interface datasheet smsc usb3280 29 revision 1.5 (11-15-07) datasheet 8.2 opmodes the opmode[1:0] pins allow control of the operating modes. the opmode[1:0] signals are normally changed on ly when the transmitter and the receiver are quiescent, i.e. when entering a test mo de or for a device initiated resume. when using opmode[1:0] = 10 (state 2), opmodes are set, and then 5 60mhz clocks later, txvalid is asserted. in this case, the sync and eop patterns are not transmitted. the only exception to this is when opmode[1:0] is set to state 2 while txvalid has been asserted (the transceiver is transmitting a packet), in order to flag a transmission error. in this case, the usb3280 has already transmitted the sync pattern so upon negation of txvalid the eop must also be transmitted to properly terminate the packet. changing the opmode[1:0] signals under all other conditions, while the transceiver is transmitting or receiving data will generate undefined results. under no circumstances should the device controlle r change opmode while the dp/dm lines are still transmitting or unpredictable changes on dp/dm are likely to occur. the same applies for termselect and xcvrselect. 8.3 test mode support table 8.2 operational modes mode[1:0] state# state name description 00 0 normal operation transceiver operates with normal usb data encoding and decoding 01 1 non-driving allows the transceiver logi c to support a soft disconnect feature which tri-states both the hs and fs transmitters, and removes any termination from the usb making it appear to an upstream port that the device has been disconnected from the bus 10 2 disable bit stuffing and nrzi encoding disables bitstuffing and nrzi encoding logic so that 1's loaded from the data bus become 'j's on the dp/dm and 0's become 'k's 11 3 reserved n/a table 8.3 usb 2.0 test modes usb 2.0 test modes usb3280 setup operational mode sie transmitted data xcvrselect & termselect se0_nak state 0 no transmit hs j state 2 all '1's hs k state 2 all '0's hs test_packet state 0 test packet data hs
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 30 smsc usb3280 datasheet 8.4 se0 handling for fs operation, idle is a j state on the bus. se0 is used as part of the eop or to indicate reset. when asserted in an eop, se0 is never asserted for more than 2 bit times. the assertion of se0 for more than 2.5us is interpreted as a rese t by the device operating in fs mode. for hs operation, idle is a se0 state on the bus. se0 is also used to reset a hs device. a hs device cannot use the 2.5us asserti on of se0 (as defined for fs operation) to indicate reset since the bus is often in this state between packets. if no bus activity (idle) is detected for more than 3ms, a hs device must determine whether the downstream fa cing port is signaling a suspend or a reset. the following section details how this determination is made. if a reset is signaled, the hs device will then initiate the hs detection handshake protocol. 8.5 reset detection if a device in hs mode detects bus inactivity for more than 3ms (t1), it reverts to fs mode. this enables the fs pull-up on the dp line in an attempt to assert a continuous fs j state on the bus. the sie must then check linestate for the se0 condition. if se0 is asserted at time t2, then the upstream port is forcing the reset state to the devic e (i.e., a driven se0). the device will then initiate the hs detection handshake protocol. figure 8.1 reset timing behavior (hs mode) table 8.4 reset timing values (hs mode) timing parameter description value hs reset t0 bus activity ceases, signaling either a reset or a suspend. 0 (reference) t1 earliest time at which the device may place itself in fs mode after bus activity stops. hs reset t0 + 3. 0ms < t1 < hs reset t0 + 3.125ms t2 sie samples linestate. if linestate = se0, then the se0 on the bus is due to a reset state. the device now enters the hs detection handshake protocol. t1 + 100s < t2 < t1 + 875s
hi-speed usb device phy with utmi interface datasheet smsc usb3280 31 revision 1.5 (11-15-07) datasheet 8.6 suspend detection if a hs device detects se0 asserted on the bus for mo re than 3ms (t1), it reverts to fs mode. this enables the fs pull-up on the dp line in an attempt to assert a continuous fs j state on the bus. the sie must then check linestate for the j condition. if j is asserted at time t2, then the upstream port is asserting a soft se0 and the usb is in a j state indicating a suspend condition. by time t4 the device must be fully suspended. figure 8.2 suspend timing behavior (hs mode) table 8.5 suspend timing values (hs mode) timing parameter description value hs reset t0 end of last bus activity, signaling either a reset or a suspend. 0 (reference) t1 the time at which the device must place itself in fs mode after bus activity stops. hs reset t0 + 3. 0ms < t1 < hs reset t0 + 3.125ms t2 sie samples linestate. if linestate = 'j', then the initial se0 on the bus (t0 - t1) had been due to a suspend state and the sie remains in hs mode. t1 + 100 s < t2 < t1 + 875s t3 the earliest time where a device can issue resume signaling. hs reset t0 + 5ms t4 the latest time that a device must actually be suspended, drawing no more than the suspend current from the bus. hs reset t0 + 10ms
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 32 smsc usb3280 datasheet 8.7 hs detection handshake the high speed detection handshake process is en tered from one of three states: suspend, active fs or active hs. the downstream facing port a sserting an se0 state on the bus initiates the hs detection handshake. depending on the initial stat e, an se0 condition can be asserted from 0 to 4 ms before initiating the hs detection handshake. these states are described in the usb 2.0 specification. there are three ways in which a device may enter the hs handshake detection process: 1. if the device is suspended and it detects an se0 state on the bus it may immediately enter the hs handshake detection process. 2. if the device is in fs mode and an se0 state is detected for more than 2.5s. it may enter the hs handshake detection process. 3. if the device is in hs mode and an se0 state is detected for more than 3.0ms. it may enter the hs handshake detection process. in hs mode, a de vice must first determine whether the se0 state is signaling a suspend or a reset condition. to do this the device reverts to fs mode by placing xcvrselect and termselect into fs mode. the device must not wait more than 3.125ms before the reversion to fs mode. after reverti ng to fs mode, no less than 100s and no more than 875s later the sie must check the linestat e signals. if a j state is detected the device will enter a suspend state. if an se0 state is de tected, then the device wil l enter the hs handshake detection process. in each case, the assertion of the se0 state on t he bus initiates the reset. the minimum reset interval is 10ms. depending on the previous mode that the bus was in, the delay between the initial assertion of the se0 state and entering the hs ha ndshake detection can be from 0 to 4ms. this transceiver design pushes as much of the responsibility for timing events on to the sie as possible, and the sie requires a stable clkout signal to perform accurate timing. in case 2 and 3 above, clkout has been running and is stable, however in case 1 the usb3280 is reset from a suspend state, and the internal oscilla tor and clocks of the transcei ver are assumed to be powered down. a device has up to 6ms after the release of suspendn to assert a minimum of a 1ms chirp k. 8.8 hs detection handshake ? fs downstream facing port upon entering the hs detection process (t0) xcvrselect and termselect are in fs mode. the dp pull-up is asserted and the hs terminations are disabled. the sie then sets opmode to disable bit stuffing and nrzi encoding , xcvrselect to hs mode, and begins the transmission of all 0's data, which asserts a hs k (chirp) on the bus (t1). the device chirp must last at least 1.0ms, and must end no later than 7.0ms after hs reset t0. at time t1 the device begins listening for a chirp sequence from the host port. if the downstream facing port is not hs capable, th en the hs k asserted by the device is ignored and the alternating sequence of hs chirp k?s and j?s is not generated. if no chir ps are detected (t4) by the device, it will enter fs mode by returning xcvrselect to fs mode.
hi-speed usb device phy with utmi interface datasheet smsc usb3280 33 revision 1.5 (11-15-07) datasheet notes: ? t0 may occur to 4ms after hs reset t0. ? the sie must assert the chirp k for 66000 clko ut cycles to ensure a 1ms minimum duration. figure 8.3 hs detection handshake timing behavior (fs mode) table 8.6 hs detection handshake timing values (fs mode) timing parameter description value t0 hs handshake begins. dp pull-up enabled, hs terminations disabled. 0 (reference) t1 device enables hs tran sceiver and asserts chirp k on the bus. t0 < t1 < hs reset t0 + 6.0ms t2 device removes chirp k from the bus. 1ms minimum width. t1 + 1.0 ms < t2 < hs reset t0 + 7.0ms t3 earliest time when downstream facing port may assert chirp kj sequence on the bus. t2 < t3 < t2+100s t4 chirp not detected by the device. device reverts to fs default state and waits for end of reset. t2 + 1.0ms < t4 < t2 + 2.5ms t5 earliest time at which host port may end reset hs reset t0 + 10ms
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 34 smsc usb3280 datasheet 8.9 hs detection handshake ? hs downstream facing port upon entering the hs detection process (t0) xcvrselect and termselect are in fs mode. the dp pull-up is asserted and the hs terminations are disabled. the sie then sets opmode to disable bit stuffing and nrzi encoding , xcvrselect to hs mode, and begins the transmission of all 0's data, which asserts a hs k (chirp) on the bus (t1). the device chirp must last at least 1.0ms, and must end no later than 7.0ms after hs reset t0. at time t1 the device begins listening for a chirp sequence from the downstream facing port. if the downs tream facing port is hs capable then it will begin generating an alternating s equence of chirp k?s and chirp j?s (t3) after the termination of the chirp from the device (t2). after the device sees t he valid chirp sequence ch irp k-j-k-j-k-j (t6), it will enter hs mode by setting termselect to hs mode (t7). figure 8.4 provides a state diagram for chirp k-j-k-j-k-j validation. prior to the end of reset (t9) the device port must terminate the sequence of chirp k? s and chirp j?s (t8) and assert se0 (t8-t9). note that the sequence of chirp k?s and chirp j?s constitutes bus activity. the chirp k-j-k-j-k-j sequence occurs too slow to propagate through the serial data path, therefore linestate signal transitions must be used by th e sie to step through the chirp k-j-k-j-k-j state diagram, where "k state" is equivalent to line state = k state and "j state" is equivalent to linestate = j state. the sie must employ a count er (chirp count) to count the number of chirp k and chirp j states. note that linestate does not fi lter the bus signals so the requirement that a bus state must be "continuously asserted for 2.5s" must be verified by the sie sampling the linestate signals. figure 8.4 chirp k-j-k-j-k-j se quence detection state diagram detect k? start chirp k-j-k-j-k-j detection inc chirp count k state !k detect j? inc chirp count j state !j chirp count != 6 & !se0 chirp count = 0 chirp count != 6 & !se0 chirp valid chirp invalid se0 chir p count
hi-speed usb device phy with utmi interface datasheet smsc usb3280 35 revision 1.5 (11-15-07) datasheet figure 8.5 hs detection handshake timing behavior (hs mode) table 8.7 reset timing values timing parameter description value t0 hs handshake begins. dp pull-up enabled, hs terminations disabled. 0 (reference) t1 device asserts chirp k on the bu s. t0 < t1 < hs reset t0 + 6.0ms t2 device removes chirp k from the bus. 1 ms minimum width. t0 + 1.0ms < t2 < hs reset t0 + 7.0ms t3 downstream facing port asserts chirp k on the bus. t2 < t3 < t2+100s t4 downstream facing port toggles chirp k to chirp j on the bus. t3 + 40s < t4 < t3 + 60s t5 downstream facing port toggles chirp j to chirp k on the bus. t4 + 40s < t5 < t4 + 60s t6 device detects downstream port chirp. t6 t7 chirp detected by the device. device removes dp pull-up and asserts hs terminations, reverts to hs default state and waits for end of reset. t6 < t7 < t6 + 500s t8 terminate host port chirp k-j sequence (repeating t4 and t5) t9 - 500s < t8 < t9 - 100s t9 the earliest time at which host port may end reset. the latest time, at whic h the device may remove the dp pull-up and assert the hs terminations, reverts to hs default state. hs reset t0 + 10ms
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 36 smsc usb3280 datasheet notes: ? t0 may be up to 4ms after hs reset t0. ? the sie must use linestate to detect the downstream port chirp sequence. ? due to the assertion of the hs termination on t he host port and fs termination on the device port, between t1 and t7 the signaling levels on the bus are higher than hs signaling levels and are less than fs signaling levels. 8.10 hs detection handshake ? suspend timing if reset is entered from a suspende d state, the internal oscillator and clocks of the transceiver are assumed to be powered down. figure 8.6 shows how clkout is used to control the duration of the chirp generated by the device. when reset is entered from a suspended state (j to se0 transition reported by linestate), suspendn is combinatorially negated at time t0 by the sie. it takes approximately 5 milliseconds for the transceiver's oscillator to stabilize. the device does not generate any transitions of the clkout signal until it is "usable" (where "usable" is defined as stable to within 10% of the nominal frequency and the duty cycle accuracy 505%). the first transition of clkout occurs at t1. the sie then sets opmode to disable bit stuffing and nrzi encoding , xcvrselect to hs mode, and must asse rt a chirp k for 6 6000 clkout cycles to ensure a 1ms minimum duration. if clkout is 10% fast (66mhz) then chirp k will be 1.0ms. if clkout is 10% slow (54 mhz) then chirp k will be 1.2ms. the 5.6ms requirement for the first clkout transition after suspendn, ensures enough time to assert a 1ms chirp k and still complete before t3. once the chirp k is completed (t3) the sie can begin looking for host chirps and use clkout to time the process. at this time , the device follows the same protocol as in section 8.9, "hs detection handshake ? hs downstream facing port" for completion of the high speed handshake.
hi-speed usb device phy with utmi interface datasheet smsc usb3280 37 revision 1.5 (11-15-07) datasheet to detect the assertion of the downstrea m chirp k's and chirp j's for 2.5us {t filt }, the sie must see the appropriate linestate signals asserted cont inuously for 165 clkout cycles. figure 8.6 hs detection handshake timing behavior from suspend table 8.8 hs detection handshake timing values from suspend timing parameter description value t0 while in suspend state an se0 is detected on the usb. hs handshake begins. d+ pull-up enabled, hs terminations disabled, suspendn negated. 0 (hs reset t0) t1 first transition of clkout. clkout "usable" (frequency accurate to 10%, duty cyc le accurate to 505). t0 < t1 < t0 + 5.6ms t2 device asserts chirp k on the bus. t1 < t2 < t0 + 5.8ms t3 device removes chirp k from the bus. (1 ms minimum width) and begins looking for host chirps. t2 + 1.0 ms < t3 < t0 + 7.0 ms t4 clk "nominal" (clkout is frequency accurate to 500 ppm, duty cycle accurate to 505). t1 < t3 < t0 + 20.0ms clk60 look for host chirps device chirp k suspendn dp/dm termselect txvalid se0 j clk power up time xcvrselect opmode 1 opmode 0 time t0 t3 t4 t1 t2
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 38 smsc usb3280 datasheet 8.11 assertion of resume in this case, an event internal to the device initiates the resume process. a device with remote wake- up capability must wait for at least 5ms after the bus is in the idle state before sending the remote wake-up resume signaling. this allows the hubs to get into their suspend state and prepare for propagating resume signaling. the device has 10ms where it can draw a non-suspend current before it must drive resume signaling. at the beginning of this period the sie may n egate suspendn, allowing the transceiver (and its oscillator) to power up and stabilize. figure 8.7 illustrates the behavior of a device returning to hs mode after being suspended. at t4, a device that was previously in fs mode would maintain termselect and xcvrselect high. to generate resume signaling (fs 'k') the device is placed in the "disable bit stuffing and nrzi encoding" operational mode (opmode [1:0] = 10), termselect and xcvrselect must be in fs mode, txvalid asserted, and all 0's data is presen ted on the data bus for at least 1ms (t1 - t2). figure 8.7 resume timing behavior (hs mode) table 8.9 resume timing values (hs mode) timing parameter description value t0 internal device event initiating the resume process 0 (reference) t1 device asserts fs 'k' on the bus to signal resume request to downstream port t0 < t1 < t0 + 10ms. t2 the device releases fs 'k' on the bus. however by this time the 'k' state is held by downstream port. t1 + 1.0ms < t2 < t1 + 15ms t3 downstream port asserts se0. t1 + 20ms t4 latest time at which a device, which was previously in hs mode, must restore hs mode after bus activity stops. t3 + 1.33s {2 low-speed bit times}
hi-speed usb device phy with utmi interface datasheet smsc usb3280 39 revision 1.5 (11-15-07) datasheet 8.12 detection of resume resume signaling always takes place in fs mode (termselect and xcvrselect = fs enabled), so the behavior for a hs device is identical to that of a fs device. the sie uses the linestate signals to determine when the usb transitions from the 'j' to the 'k' state and finally to the terminating fs eop (se0 for 1.25us-1.5s.). the resume signaling (fs 'k') will be asserted for at least 20ms. at the beginning of this period the sie may negate suspendn, allowing the transceiver (and its oscillator) to power up and stabilize. the fs eop condition is relatively short. sies that simply look for an se0 condition to exit suspend mode do not necessarily give the transceiver? s clock generator enough time to stabilize. it is recommended that all sie implementations key off t he 'j' to 'k' transition for exiting suspend mode (suspendn = 1). and within 1.25s after the transi tion to the se0 state (low-speed eop) the sie must enable normal operation, i.e. enter hs or fs mode depending on the mode the device was in when it was suspended. if the device was in fs mode: then the sie leaves the fs terminations enabled. after the se0 expires, the downstream port will assert a j state for one low-speed bit time, and the bus will enter a fs idle state (maintained by the fs terminations). if the device was in hs mode: then the sie must swit ch to the fs terminations before the se0 expires ( < 1.25s). after the se0 expires, the bus will then enter a hs idle state (maintained by the hs terminations). 8.13 hs device attach figure 8.8 demonstrates the timing of the usb3280 control signals during a device attach event. when a hs device is attached to an upstream port, po wer is asserted to the device and the device sets xcvrselect and termselect to fs mode (time t1). v bus is the +5v power available on the usb cable. device reset in figure 8.8 indicates that v bus is within normal operational range as defined in the usb 2.0 specification. the assertion of device reset (t0) by the upstream port will initialize the devic e. by monitoring linestate, the sie state machine knows to set the xcvrselect and term select signals to fs mode (t1). the standard fs technique of using a pull-up resistor on dp to signal the attach of a fs device is employed. the sie must then ch eck the linestate signals for se0. if linestate = se0 is asserted at time t2 then the upstream port is forcing the re set state to the device (i .e. driven se0). the device will then reset itself before initiating the hs detection handshake protocol.
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 40 smsc usb3280 datasheet figure 8.8 device attach behavior table 8.10 attach and reset timing values timing parameter description value t0 vbus valid. 0 (reference) t1 maximum time from vbus valid to when the device must signal attach. t0 + 100ms < t1 t2 (hs reset t0) debounce interval. the device now enters the hs detection handshake protocol. t1 + 100ms < t2
hi-speed usb device phy with utmi interface datasheet smsc usb3280 41 revision 1.5 (11-15-07) datasheet 8.14 application diagram figure 8.9 usb3280 application diagram utmi usb power txvalid txready rxactive rxvalid rxerror xcvrselect termselect suspendn reset opmode 0 opmode 1 linestate 0 linestate 1 clkout data 0 data 1 data 2 data 3 data 4 data 5 data 6 data 7 xi xo dp dm vdda1.8 vdd1.8 vdd1.8 vdd3.3 vdd3.3 reg_en vdd3.3 vdd3.3 vdd3.3 vss usb-b gnd vdd3.3 1? 24 mhz crystal c load c load 26 25 24 23 22 21 20 19 32 31 33 17 30 7 34 35 10 18 29 1 2 4 6 13 12 16 15 14 8 9 rbias 36 12k 5 3 11 27 28 exposed pad 4.7uf ceramic 4.7uf ceramic 4.7uf ceramic 0.1uf and/or 0.01uf ceramic capacitors are also required on power supply pins.
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 42 smsc usb3280 datasheet chapter 9 package outline figure 9.1 usb3280-aezg 36-pin qfn package outline and para meters, 6 x 6 x 0.90 mm body (lead-free rohs compliant) catalog part exposed pad b added "preliminary" note 11/6/03 s.k.iliev c deleted "preliminary" note 6/30/04 s.k.iliev d new smsc drawing format & adding 3-d view 12/7/04 s.k.iliev e l(min) from 0.35 to 0.50, d2/e2 from 1.75 - 4.25 to 3.55-3.70-3.85 4/5/05 s.k.iliev f added paragraphs 1 to 6 in main spec body & dwg as attachment 7/11/05 s.k.iliev side view 3-d views top view 3 2 bottom view notes: 1. all dimensions are in millimeter. 2. position tolerance of each terminal is 0.05mm at maximum material condition. dimensions "b" applies to plated terminals and it is measured between 0.15 and 0.30 mm from the terminal tip. 3. details of terminal #1 identifier are optional but must be located within the area indicated. 4. coplanarity zone applies to exposed pad and terminals. e2 e e1 d d1 terminal #1 identifier area (d1/2 x e1/2) 36x b 36x l terminal #1 identifier area (d/2 x e/2) d2 e 3 a1 a initial release 6/13/03 s.k.iliev a2 a 4x 45x0.6 max (optional) 36x 0.2 min decimal x.x x.xx x.xxx material finish std compliance third angle projection print with "sc ale to fit" do not scale drawing appr oved angular unless otherwise specified dimensions are in millimeters and tolerances are: di m a nd to l p er a sm e y14.5m - 1994 drawn checked name scale 80 arkay drive h aup paug e, ny 11788 usa dwg number title date sheet rev revision history description revision released by date s.k.iliev s.k.iliev s.k.iliev 1 - - 0.025 0.05 0.1 12/6/04 1:1 12/6/04 12/6/04 f jedec: mo-220 1 of 1 36 terminal qfn, 6x6mm body, 0.5mm pitch package outline mo-36-qfn-6x6 4 ccc c 4 c a3 4x 0-12 d2 / e2 variations
hi-speed usb device phy with utmi interface datasheet smsc usb3280 43 revision 1.5 (11-15-07) datasheet figure 9.2 qfn, 6x6 tape & reel
hi-speed usb device phy with utmi interface datasheet revision 1.5 (11-15-07) 44 smsc usb3280 datasheet note: standard reel size is 3000 pieces per reel. figure 9.3 reel dimensions

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